Company vault
Semiconductor and software — low-level concepts, C++, and parallelism in Oregon and Arizona.
Questions
105
Reported in Intel USA engineering loops. Core OOP concepts asked in almost every fresher technical screen.
Reported in Intel USA engineering loops. Fundamental operating-system question for entry-level engineering roles.
Reported in Intel USA engineering loops. Classic SQL screening question testing subqueries, window functions, or ordering.
Reported in Intel USA engineering loops. DBMS fundamentals covering 1NF through 3NF and when to denormalize.
Reported in Intel USA engineering loops. Networking basics question covering transport-layer reliability and use cases.
Reported in Intel USA engineering loops. HR opener testing motivation, research, and alignment with the role.
Reported in Intel USA engineering loops. Behavioral HR question assessing self-awareness and growth mindset.
Reported in Intel USA engineering loops. OS concept linking paging, address translation, and process isolation.
Reported in Intel USA engineering loops. Classic array + hash map problem testing optimal time–space trade-offs.
Reported in Intel USA engineering loops. Foundational search algorithm with clear loop invariants and edge cases.
Reported in Intel USA engineering loops. Pointer manipulation staple for junior coding interviews.
Reported in Intel USA engineering loops. Graph traversal question covering shortest paths, connectivity, and complexity.
Reported in Intel USA engineering loops. Tree recursion warm-up that often leads to balanced-tree and diameter follow-ups.
Reported in Intel USA engineering loops. Sliding window pattern for substring problems with hash set or map tracking.
Reported in Intel USA engineering loops. Sort-and-sweep array problem common in calendar and scheduling interviews.
Reported in Intel USA engineering loops. Introductory dynamic programming problem isomorphic to Fibonacci.
Reported in Intel USA engineering loops. Hash map plus doubly linked list problem bridging DSA and system components.
Reported in Intel USA engineering loops. Classic DP testing tabulation, space optimization, and item selection reconstruction.
Reported in Intel USA engineering loops. Graph algorithm for non-negative edge weights using priority queue.
Reported in Intel USA engineering loops. Foundational system design covering APIs, encoding, storage, and read-heavy scaling.